Generally, a flash memory is an Electrically Erasable Programmable Read Only Memory (EEPROM) capable of electrically overwriting data. Data or information stored in the flash memory is considered non-volatile, because it is not lost when the power is turned off, unlike dynamic RAM (DRAM) or static RAM (SRAM).
The flash memory element may maintain written data for a long period. Flash memory may require a high degree of component integration to remain competitive with other memory devices. In order to manufacture a flash memory with a smaller feature size, a technique for applying a threshold line-width of less than 90 nm to a manufacturing process of the flash memory (hereinafter referred to as 90 nm-grade technique) may be used.
A 90 nm-grade technique may be applied to the manufacturing process of the flash memory to implement large scale integration and higher precision flash memory. Demand for a fabrication technique capable of correctly pre-recognizing a relatively small change in the fabrication process is rapidly increasing. When a 90 nm-grade technique is applied to the fabrication of flash memory, defects caused by the trench isolation step height induced (TRISI) effect may occur in the shallow trench isolation (STI) area for defining an active area of a semiconductor substrate.
Due to a topology of the STI layer formed over a substrate in a narrow active area, a thickness of a polysilicon layer used as a gate may not be evenly maintained or managed. Variations in a threshold voltage of the memory cell may cause undesirable results. Referring to FIG. 1, a plurality of STI layers 32 for defining the active area 22 are formed over the semiconductor substrate 10. To implement a 90-nm grade technique, the interval (i.e., the active area 22) between the STI layers 32 is narrowed. The STI layers 32 are slightly projected over the substrate 10, such that the profile of the polysilicon layer 40 formed by interposing the gate oxide layer 42 between the polysilicon layer 40 and the substrate 10 is uneven. As a result, variation in a threshold voltage of the memory cell may become large, and the TRISI effect deteriorates characteristics of the products.
To resolve issues associated with the TRISI effect, the step height of the STI layer 32 may be maintained under about 70 nm. It may be difficult to measure or inspect the step height (H) of the STI layer during the manufacturing process of the semiconductor device.
The unevenness of the STI step-height may increase a current leakage between the active layer and the STI layer. If current leakage occurs between the active layer and the STI layer, data loss or corruption may occur. Therefore, a method for effectively monitoring the unevenness of the STI step-height may help improve the overall manufacture of flash memory.